1. Field of the Invention
The present invention relates to packaging technologies, and more particularly, to an electronic package structure and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. To meet the miniaturization requirement of semiconductor packages, packaging substrates for carrying semiconductor chips are becoming thinner.
FIGS. 1A to 1D are schematic cross-sectional views showing a method for fabricating a coreless semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a circuit layer 11 is formed on a carrier 10. The circuit layer 11 has a die attach pad 111 and a plurality of conductive pads 112 around the die attach pad 111.
Referring to FIG. 1B, a semiconductor chip 12 is disposed on the die attach pad 111 and electrically connected to the conductive pads 112 through a plurality of bonding wires 120. Then, a first insulating layer 13 is formed on the carrier 10 to encapsulate the semiconductor chip 12 and the bonding wires 120.
Referring to FIG. 1C, the carrier 10 is removed to expose the circuit layer 11 and a lower surface of the first insulating layer 13.
Referring to FIG. 1D, a surface treatment layer 14 is formed on the exposed circuit layer 11, and then a second insulating layer 15 is formed on the lower surface of the first insulating layer 13. Portions of the surface treatment layer 14 are exposed from the second insulating layer 15. Thereafter, a plurality of conductive elements 16 such as solder balls are formed on the exposed portions of the surface treatment layer 14, and a singulation process is performed to obtain a semiconductor package 1.
However, since the circuit layer 11 is flush with the lower surface of the first insulating layer 13, when an SMT (Surface Mounting Technology) process is performed to mount the semiconductor package 1 on a circuit board, it is difficult to align the conductive elements 16 with contacts of the circuit board, thus reducing the yield of the SMT process.
Therefore, there is a need to provide an electronic package structure and a fabrication method thereof so as to overcome the above-described drawbacks.